1. Field of the Invention
The present invention relates to a semiconductor memory device having a capacitor and a method for manufacturing the same, and more particularly to a highly integrated semiconductor memory device having a capacitor which includes a double-cylindrical storage electrode for high reliability and large cell capacitance for memory cells and a method for manufacturing the same.
2 Description of Related Art
The decrease in cell capacitance caused by reduced memory cell area is a serious obstruction when increasing the packing density in dynamic random access memories (DRAMs).
Generally, in a 64 Mb DRAM having a 1.5 .mu.m.sup.2 memory cell area employing an ordinary two-dimensional stacked capacitor cell, sufficient cell capacitance cannot be obtained even though a higher dielectric constant material, (e.g., tantalum oxide (Ta.sub.2 O.sub.5)), is used. Therefore, stacked capacitors having a three-dimensional structure have been suggested to improve cell capacitance. Such stacked capacitors include, for example, double-stacked, fin-structured, cylindrical, spread-stacked, and box-structured capacitors.
Since both the outer and inner surfaces can be utilized as an effective capacitor area, the cylindrical electrode structure is favorably suited to the three-dimensional stacked capacitor, especially for an integrated memory cell which is 64 Mb or higher. Also, an improved stacked capacitor has recently been presented, wherein pillars or another inner cylinder are formed in the interior of the main cylinder. Not only may both inner and outer surfaces of the cylinder be utilized to increase the effective capacitor area, but also the outer surface of the pillars or the inner cylinder formed in the interior of the cylinder.
For example, T. Kaga et al. have suggested a crown-shaped stacked capacitor (see "Crown-Shaped Stacked-Capacitor Cell for 1.5 V Operation 64-Mb DRAM's" by T. Kaga et al., IEEE Transactions on Electron Devices Vol. 38 No. 2, February 1991, pp 255-260), wherein an inner cylinder is formed in the interior of an outer cylinder. This is hereinafter referred to as a double-cylindrical capacitor.
FIGS. 1 to 4 are sectional views for illustrating a conventional manufacturing method of the double-cylindrical stacked capacitor of a semiconductor memory device, as described in the above T. Kaga et al. paper.
FIG. 1 illustrates a step of forming a polycrystalline silicon layer 34 for forming an outer cylinder and a spacer 36. Particularly, after forming transistors on an active region of a semiconductor substrate, an insulating layer 19 is formed on the whole surface of the resultant structure for insulating the transistors from other conductive layers (which will be formed in subsequent steps). Thereafter, a planarization layer 22 is formed on the insulting layer 19, then a contact hole is formed for connecting a storage electrode with source region 14 by partially removing planarization layer 22 and insulating layer 19 formed on source region 14. Then, a pillar electrode 30 which fills the contact hole is formed by depositing and etching-back a polycrystalline silicon layer. Then a silicon nitride layer 26 and silicon dioxide layer 32 are successively formed on the surface of the thus-obtained resultant structure. Thereafter, a well is formed by partially removing silicon dioxide layer 32 and silicon nitride layer 26 formed over pillar electrode 30. The well is formed so that it defines individual cell units and exposes the surface of pillar electrode 30. Then, a polycrystalline silicon layer 34 for forming the outer cylinder is formed on the surface of the resultant structure. And then another silicon dioxide layer is formed on polycrystalline silicon layer 34 and is anisotropically etched, thereby forming a spacer 36 on an interior sidewall of each well.
FIG. 2 illustrates a step of forming a polycrystalline silicon layer 38 and a silicon dioxide layer 40. After the step of FIG. 1, polycrystalline silicon layer 38 for forming an outer cylinder is formed on the surface of the resultant structure in FIG. 1 on which spacer 36 has been formed. Then, silicon dioxide layer 40 is formed on the surface of the resultant structure so as to cover polycrystalline silicon layer 38.
FIG. 3 illustrates a step of forming a storage electrode 100. After the steps illustrated in FIG. 2, silicon dioxide layer 40 is etched back. The etch-back is performed on the surface of the structure until a portion of polycrystalline silicon layer 38 is exposed. Then, the exposed polycrystalline silicon layer 38 is in turn anisotropically etched to thereby expose a portion of polycrystalline silicon layer 34, which is likewise partially removed by anisotropically etching, thereby forming a storage electrode 100 comprised of outer cylinder 34' and inner cylinder 38'. Here, reference numeral 40' denotes an oxide residue formed in the inner cylinder results from the etching back of silicon dioxide layer 40.
FIG. 4 illustrates a step of completing a capacitor. After removing oxide residue 40', spacer 36 and silicon dioxide layer 32, a dielectric layer 110 is formed on the whole surface of storage electrode 100. A plate electrode 120 is then formed by depositing a polycrystalline silicon material on the whole surface of the resultant, thereby completing a capacitor comprised of storage electrode 100, dielectric film 110 and plate electrode 120.
According to the above conventional method for manufacturing a capacitor of a semiconductor memory device, a double cylinder-type storage electrode having an inner cylinder inside an outer cylinder can be manufactured, thereby enlarging the cell capacitance of a semiconductor memory device. However, this method has certain drawbacks.
First, as shown in FIG. 1, after the contact hole for the formation of the pillar electrode is formed, the hole is filled a polycrystalline silicon. Precise filling of the contact hole with the polycrystalline silicon is crucial because the shape of the outer cylinder formed over the contact hole depends on the state in which the polycrystalline silicon fills the contact hole. This process is very difficult to achieve with the precision required.
Second, as shown in FIG. 1, when forming the well by anisotropically etching silicon dioxide layer 32, the well is apt to be formed so as to have a sloped sidewall, which causes voids between cells when subsequently forming the corresponding plate electrode. Thus, the electrical characteristics of the memory device are potentially deteriorated.
Third, etching-back silicon dioxide layer 40 as shown in FIG. 3 is difficult to control with precision, so uniform cell capacitance cannot be easily obtained.
Fourth, as shown in FIG. 2, since the storage electrode is the result of polycrystalline silicon layers 34 and 38 and pillar electrode portion 30, a native oxide layer forms on the opposing surfaces of the polycrystalline silicon layers. This undesireably increases the series electrical resistance. It also decreases the interlayer adherence so that fragments of the polycrystalline silicon layer may be lost when force is applied thereto, for example, when spinning the wafer.
Fifth, since the double-cylindrical electrode thus obtained has sharply edged ends, excessive leakage currents are created.